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| author |   Dave Jiang <dave.jiang@intel.com> | 2025-03-14 14:27:17 -0700 |
|---|---|---|
| committer | Dave Jiang <dave.jiang@intel.com> | 2025-03-14 14:27:17 -0700 |
| commit | 9387c6aec0b69cc9346b84838c04c6e550c016c1 (patch) | |
| tree | 732c8b8dc55d3e03c6a8facfb23a51af21230026 /scripts/lib/kdoc/kdoc_re.py | |
| parent | cxl: Cleanup partition size and perf helpers (diff) | |
| parent | cxl/pci: Add trace logging for CXL PCIe Port RAS errors (diff) | |
| download | wireguard-linux-9387c6aec0b69cc9346b84838c04c6e550c016c1.tar.xz wireguard-linux-9387c6aec0b69cc9346b84838c04c6e550c016c1.zip | |
Merge branch 'for-6.15/fw-first-error-logging' into cxl-for-next2
Add logging support for CXL CPER endpoint and port protocol errors.
Including the 2 patches that was completed later.
Link: https://lore.kernel.org/linux-cxl/20250123084421.127697-1-Smita.KoralahalliChannabasappa@amd.com/
Link: https://lore.kernel.org/linux-cxl/20250310223839.31342-1-Smita.KoralahalliChannabasappa@amd.com/
Diffstat (limited to 'scripts/lib/kdoc/kdoc_re.py')
0 files changed, 0 insertions, 0 deletions