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| author |   Tudor Ambarus <tudor.ambarus@microchip.com> | 2021-12-09 14:36:42 +0200 |
|---|---|---|
| committer |   Nicolas Ferre <nicolas.ferre@microchip.com> | 2021-12-13 14:48:04 +0100 |
| commit | 0081a525ceef14e950172def4af14c3f652fb4a2 (patch) | |
| tree | 1203b7b7ff3bced7284e26e1fb91cfe691863ee9 /scripts/mod/file2alias.c | |
| parent | ARM: dts: at91: sama5d2: Name the qspi clock (diff) | |
| download | wireguard-linux-0081a525ceef14e950172def4af14c3f652fb4a2.tar.xz wireguard-linux-0081a525ceef14e950172def4af14c3f652fb4a2.zip | |
ARM: dts: at91: sama7g5: Add QSPI nodes
sama7g5 embedds 2 instances of QSPI controller:
1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
and OctaFlash Protocols Supported.
2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20211209123643.341892-1-tudor.ambarus@microchip.com
Diffstat (limited to 'scripts/mod/file2alias.c')
0 files changed, 0 insertions, 0 deletions