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| author |   Jiri Kosina <jkosina@suse.cz> | 2022-03-23 09:58:40 +0100 |
|---|---|---|
| committer | Jiri Kosina <jkosina@suse.cz> | 2022-03-23 09:58:40 +0100 |
| commit | b690490d6d466972ade172ee2e7f6ffa49e7e910 (patch) | |
| tree | 50a93da28c9128e19eb7a3038aecf75dab6b36e1 /scripts/mod | |
| parent | HID: intel-ish-hid: Use dma_alloc_coherent for firmware update (diff) | |
| parent | HID: amd_sfh: Remove useless DMA-32 fallback configuration (diff) | |
| download | wireguard-linux-b690490d6d466972ade172ee2e7f6ffa49e7e910.tar.xz wireguard-linux-b690490d6d466972ade172ee2e7f6ffa49e7e910.zip | |
Merge branch 'for-5.18/amd-sfh' into for-linus
- dead code elimination (Christophe JAILLET)
Diffstat (limited to 'scripts/mod')
| -rw-r--r-- | scripts/mod/modpost.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index cb8ab7d91d30..6bfa33217914 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -1830,6 +1830,14 @@ static int addend_mips_rel(struct elf_info *elf, Elf_Shdr *sechdr, Elf_Rela *r) return 0; } +#ifndef EM_RISCV +#define EM_RISCV 243 +#endif + +#ifndef R_RISCV_SUB32 +#define R_RISCV_SUB32 39 +#endif + static void section_rela(const char *modname, struct elf_info *elf, Elf_Shdr *sechdr) { @@ -1866,6 +1874,13 @@ static void section_rela(const char *modname, struct elf_info *elf, r_sym = ELF_R_SYM(r.r_info); #endif r.r_addend = TO_NATIVE(rela->r_addend); + switch (elf->hdr->e_machine) { + case EM_RISCV: + if (!strcmp("__ex_table", fromsec) && + ELF_R_TYPE(r.r_info) == R_RISCV_SUB32) + continue; + break; + } sym = elf->symtab_start + r_sym; /* Skip special sections */ if (is_shndx_special(sym->st_shndx)) |