diff options
| author |   Vijendar Mukunda <Vijendar.Mukunda@amd.com> | 2023-06-26 16:23:52 +0530 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2023-06-26 13:28:59 +0100 |
| commit | 46b50e514b191ae15789cccabace5b6040c9278e (patch) | |
| tree | 5f04f01a50fd367d62148239df0e0018dbc8997e /sound/soc/amd/ps/ps-sdw-dma.c | |
| parent | ASoC: amd: ps: fix for position register set for AUDIO0 RX stream (diff) | |
| download | wireguard-linux-46b50e514b191ae15789cccabace5b6040c9278e.tar.xz wireguard-linux-46b50e514b191ae15789cccabace5b6040c9278e.zip | |
ASoC: amd: ps: add comments for DMA register mapping
Add comments for DMA register mapping for both the SoundWire manager
instances.
Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
Link: https://lore.kernel.org/r/20230626105356.2580125-4-Vijendar.Mukunda@amd.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/amd/ps/ps-sdw-dma.c')
| -rw-r--r-- | sound/soc/amd/ps/ps-sdw-dma.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/sound/soc/amd/ps/ps-sdw-dma.c b/sound/soc/amd/ps/ps-sdw-dma.c index 3ab41bd1fce2..000ab5d96815 100644 --- a/sound/soc/amd/ps/ps-sdw-dma.c +++ b/sound/soc/amd/ps/ps-sdw-dma.c @@ -39,6 +39,11 @@ static struct sdw_dma_ring_buf_reg sdw0_dma_ring_buf_reg[ACP63_SDW0_DMA_MAX_STRE ACP_AUDIO2_RX_LINEARPOSITIONCNTR_LOW, ACP_AUDIO2_RX_LINEARPOSITIONCNTR_HIGH} }; +/* + * SDW1 instance supports one TX stream and one RX stream. + * For TX/RX streams DMA registers programming for SDW1 instance, it uses ACP_P1_AUDIO1 register + * set as per hardware register documentation + */ static struct sdw_dma_ring_buf_reg sdw1_dma_ring_buf_reg[ACP63_SDW1_DMA_MAX_STREAMS] = { {ACP_P1_AUDIO1_TX_DMA_SIZE, ACP_P1_AUDIO1_TX_FIFOADDR, ACP_P1_AUDIO1_TX_FIFOSIZE, ACP_P1_AUDIO1_TX_RINGBUFSIZE, ACP_P1_AUDIO1_TX_RINGBUFADDR, @@ -59,6 +64,12 @@ static u32 sdw0_dma_enable_reg[ACP63_SDW0_DMA_MAX_STREAMS] = { ACP_SW0_AUDIO2_RX_EN, }; +/* + * SDW1 instance supports one TX stream and one RX stream. + * For TX/RX streams DMA enable register programming for SDW1 instance, + * it uses ACP_SW1_AUDIO1_TX_EN and ACP_SW1_AUDIO1_RX_EN registers + * as per hardware register documentation. + */ static u32 sdw1_dma_enable_reg[ACP63_SDW1_DMA_MAX_STREAMS] = { ACP_SW1_AUDIO1_TX_EN, ACP_SW1_AUDIO1_RX_EN, |