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| author |   Codrin Ciubotariu <codrin.ciubotariu@microchip.com> | 2019-06-27 15:02:08 +0300 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2019-06-28 13:40:37 +0100 |
| commit | 8af6b2291e054773e2e58b2e5dbc06e981d14296 (patch) | |
| tree | 09f8e14f5d1b191e7278746739bf396a917cb45a /sound/soc/codecs/ad193x.c | |
| parent | ASoC: codecs: ad193x: Group register initialization at probe (diff) | |
| download | wireguard-linux-8af6b2291e054773e2e58b2e5dbc06e981d14296.tar.xz wireguard-linux-8af6b2291e054773e2e58b2e5dbc06e981d14296.zip | |
ASoC: codecs: ad193x: Reset used registers at probe
Since the ad193x codecs have no software reset, we have to reinitialize the
registers after a hardware reset to assure no previous values are kept.
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/ad193x.c')
| -rw-r--r-- | sound/soc/codecs/ad193x.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/sound/soc/codecs/ad193x.c b/sound/soc/codecs/ad193x.c index f3bab8fe3579..9615e786d049 100644 --- a/sound/soc/codecs/ad193x.c +++ b/sound/soc/codecs/ad193x.c @@ -427,12 +427,22 @@ static void ad193x_reg_default_init(struct ad193x_priv *ad193x) { 0, 0x99 }, /* PLL_CLK_CTRL0: pll input: mclki/xi 12.288Mhz */ { 1, 0x04 }, /* PLL_CLK_CTRL1: no on-chip Vref */ { 2, 0x40 }, /* DAC_CTRL0: TDM mode */ + { 3, 0x00 }, /* DAC_CTRL1: reset */ { 4, 0x1A }, /* DAC_CTRL2: 48kHz de-emphasis, unmute dac */ { 5, 0x00 }, /* DAC_CHNL_MUTE: unmute DAC channels */ + { 6, 0x00 }, /* DAC_L1_VOL: no attenuation */ + { 7, 0x00 }, /* DAC_R1_VOL: no attenuation */ + { 8, 0x00 }, /* DAC_L2_VOL: no attenuation */ + { 9, 0x00 }, /* DAC_R2_VOL: no attenuation */ + { 10, 0x00 }, /* DAC_L3_VOL: no attenuation */ + { 11, 0x00 }, /* DAC_R3_VOL: no attenuation */ + { 12, 0x00 }, /* DAC_L4_VOL: no attenuation */ + { 13, 0x00 }, /* DAC_R4_VOL: no attenuation */ }; const struct ad193x_reg_default reg_adc_init[] = { { 14, 0x03 }, /* ADC_CTRL0: high-pass filter enable */ { 15, 0x43 }, /* ADC_CTRL1: sata delay=1, adc aux mode */ + { 16, 0x00 }, /* ADC_CTRL2: reset */ }; int i; |