diff options
| author |   Dan Murphy <dmurphy@ti.com> | 2020-04-27 15:36:08 -0500 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2020-04-28 13:33:57 +0100 |
| commit | be8499c48f115b912f5747c420f66a5e2c31defe (patch) | |
| tree | 283aa3a79e62cf02ec9563a89215593ce623c82f /sound/soc/codecs/tlv320adcx140.c | |
| parent | ASoC: davinci-mcasp: Fix dma_chan refcnt leak when getting dma type (diff) | |
| download | wireguard-linux-be8499c48f115b912f5747c420f66a5e2c31defe.tar.xz wireguard-linux-be8499c48f115b912f5747c420f66a5e2c31defe.zip | |
ASoC: tlv320adcx140: Fix mic gain registers
Fix the mic gain registers for channels 2-4.
The incorret register was being set as it was touching the CH1 config
registers.
Fixes: 37bde5acf040 ("ASoC: tlv320adcx140: Add the tlv320adcx140 codec driver family")
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20200427203608.7031-1-dmurphy@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/tlv320adcx140.c')
| -rw-r--r-- | sound/soc/codecs/tlv320adcx140.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/sound/soc/codecs/tlv320adcx140.c b/sound/soc/codecs/tlv320adcx140.c index 38897568ee96..0f713efde046 100644 --- a/sound/soc/codecs/tlv320adcx140.c +++ b/sound/soc/codecs/tlv320adcx140.c @@ -511,11 +511,11 @@ static const struct snd_soc_dapm_route adcx140_audio_map[] = { static const struct snd_kcontrol_new adcx140_snd_controls[] = { SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0, adc_tlv), - SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH1_CFG2, 2, 42, 0, + SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0, adc_tlv), - SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH1_CFG3, 2, 42, 0, + SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0, adc_tlv), - SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH1_CFG4, 2, 42, 0, + SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0, adc_tlv), SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0, |