diff options
| author |   Shengjiu Wang <shengjiu.wang@nxp.com> | 2023-11-22 09:42:53 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2023-11-22 12:04:26 +0000 |
| commit | c33fd110424dfcb544cf55a1b312f43fe1918235 (patch) | |
| tree | 7152254fab28402d3fb91032b54813fc8d953203 /sound/soc/fsl | |
| parent | ASoC: fsl_sai: Fix no frame sync clock issue on i.MX8MP (diff) | |
| download | wireguard-linux-c33fd110424dfcb544cf55a1b312f43fe1918235.tar.xz wireguard-linux-c33fd110424dfcb544cf55a1b312f43fe1918235.zip | |
ASoC: fsl_xcvr: Enable 2 * TX bit clock for spdif only case
The bit 10 in TX_DPTH_CTRL register controls the TX clock rate.
If this bit is set, TX datapath clock should be = 2* TX bit rate.
If this bit is not set, TX datapath clock should be 10* TX bit rate.
As the spdif only case, we always use 2 * TX bit clock, so
this bit need to be set.
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1700617373-6472-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/fsl')
| -rw-r--r-- | sound/soc/fsl/fsl_xcvr.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/sound/soc/fsl/fsl_xcvr.c b/sound/soc/fsl/fsl_xcvr.c index fa0a15263c66..77f8e2394bf9 100644 --- a/sound/soc/fsl/fsl_xcvr.c +++ b/sound/soc/fsl/fsl_xcvr.c @@ -414,6 +414,16 @@ static int fsl_xcvr_prepare(struct snd_pcm_substream *substream, switch (xcvr->mode) { case FSL_XCVR_MODE_SPDIF: + if (xcvr->soc_data->spdif_only && tx) { + ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_TX_DPTH_CTRL_SET, + FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM, + FSL_XCVR_TX_DPTH_CTRL_BYPASS_FEM); + if (ret < 0) { + dev_err(dai->dev, "Failed to set bypass fem: %d\n", ret); + return ret; + } + } + fallthrough; case FSL_XCVR_MODE_ARC: if (tx) { ret = fsl_xcvr_en_aud_pll(xcvr, fout); |