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| author |   Cezary Rojewski <cezary.rojewski@intel.com> | 2022-03-11 16:35:41 +0100 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-03-11 16:24:07 +0000 |
| commit | b27f452317236b0cbaa94c4498f8241e2ad871b1 (patch) | |
| tree | e67ea17c5e924c67119ee219d1334db2690a1929 /sound/soc/intel/avs/registers.h | |
| parent | ASoC: Intel: avs: Dynamic firmware resources management (diff) | |
| download | wireguard-linux-b27f452317236b0cbaa94c4498f8241e2ad871b1.tar.xz wireguard-linux-b27f452317236b0cbaa94c4498f8241e2ad871b1.zip | |
ASoC: Intel: avs: General code loading flow
Code loading is a complex procedure and requires combined effort of DMA
and IPCs. With IPCs already in place, lay out ground for specific DMA
transfer operations.
Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com>
Signed-off-by: Cezary Rojewski <cezary.rojewski@intel.com>
Link: https://lore.kernel.org/r/20220311153544.136854-15-cezary.rojewski@intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/intel/avs/registers.h')
| -rw-r--r-- | sound/soc/intel/avs/registers.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/sound/soc/intel/avs/registers.h b/sound/soc/intel/avs/registers.h index 775701454a28..73699d46821b 100644 --- a/sound/soc/intel/avs/registers.h +++ b/sound/soc/intel/avs/registers.h @@ -9,6 +9,12 @@ #ifndef __SOUND_SOC_INTEL_AVS_REGS_H #define __SOUND_SOC_INTEL_AVS_REGS_H +#define AZX_PCIREG_PGCTL 0x44 +#define AZX_PCIREG_CGCTL 0x48 +#define AZX_PGCTL_LSRMD_MASK BIT(4) +#define AZX_CGCTL_MISCBDCGE_MASK BIT(6) +#define AZX_VS_EM2_L1SEN BIT(13) + /* Intel HD Audio General DSP Registers */ #define AVS_ADSP_GEN_BASE 0x0 #define AVS_ADSP_REG_ADSPCS (AVS_ADSP_GEN_BASE + 0x04) |