diff options
| author |   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2023-08-22 23:51:02 +0000 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2023-08-23 13:53:29 +0100 |
| commit | 4acdf9aedd5624aae9335d70a9324d5aaec4034d (patch) | |
| tree | 2570953a361960f50e509806f7d02ec45add07d9 /sound/soc/sh | |
| parent | ASoC: rsnd: remove default division of clock out (diff) | |
| download | wireguard-linux-4acdf9aedd5624aae9335d70a9324d5aaec4034d.tar.xz wireguard-linux-4acdf9aedd5624aae9335d70a9324d5aaec4034d.zip | |
ASoC: rsnd: setup BRGCKR/BRRA/BRRB on rsnd_adg_clk_control()
Current adg.c will configure BRGCKR/BRRA/BRRB to output clock
when it start sound. OTAH, rsnd_adg_clk_enable() will enables
clk_a/b/c when driver was probed.
But it is strange, these should be set in the same time.
This patch fixup it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87h6oqzlei.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/sh')
| -rw-r--r-- | sound/soc/sh/rcar/adg.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/sound/soc/sh/rcar/adg.c b/sound/soc/sh/rcar/adg.c index 25d3316a50d1..230c48648af3 100644 --- a/sound/soc/sh/rcar/adg.c +++ b/sound/soc/sh/rcar/adg.c @@ -358,8 +358,6 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) ckr = 0x80000000; /* BRGB output = 48kHz */ rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr | ckr); - rsnd_mod_write(adg_mod, BRRA, adg->brga); - rsnd_mod_write(adg_mod, BRRB, adg->brgb); dev_dbg(dev, "CLKOUT is based on BRG%c (= %dHz)\n", (ckr) ? 'B' : 'A', @@ -372,9 +370,16 @@ int rsnd_adg_ssi_clk_try_start(struct rsnd_mod *ssi_mod, unsigned int rate) void rsnd_adg_clk_control(struct rsnd_priv *priv, int enable) { struct rsnd_adg *adg = rsnd_priv_to_adg(priv); + struct rsnd_mod *adg_mod = rsnd_mod_get(adg); struct clk *clk; int i; + if (enable) { + rsnd_mod_bset(adg_mod, BRGCKR, 0x80770000, adg->ckr); + rsnd_mod_write(adg_mod, BRRA, adg->brga); + rsnd_mod_write(adg_mod, BRRB, adg->brgb); + } + for_each_rsnd_clkin(clk, adg, i) { if (enable) { clk_prepare_enable(clk); |