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| author |   Axel Lin <axel.lin@ingics.com> | 2015-08-12 11:10:49 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2015-08-14 17:31:19 +0100 |
| commit | fbf917e14eb65689ad80290170f7d615be711fb7 (patch) | |
| tree | b0cf8bd6ee7d52da7cc882cb6050b3f468ac5d1b /sound/soc/soc-core.c | |
| parent | ASoC: cs42l73: Fix mask for setting CS42L73_SP_3ST bit (diff) | |
| download | wireguard-linux-fbf917e14eb65689ad80290170f7d615be711fb7.tar.xz wireguard-linux-fbf917e14eb65689ad80290170f7d615be711fb7.zip | |
ASoC: cs42l73: Use case range at appropriate place
The readable registers are in continuous ranges: 0x01 ~ 0x03, 0x05 ~ 0x5f.
Use case range syntax makes the code shorter with better readability when
we have a large number of continuous switch cases.
No functional change with this patch.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/soc-core.c')
0 files changed, 0 insertions, 0 deletions