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| author |   Mark Brown <broonie@kernel.org> | 2023-02-24 14:03:58 +0000 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2023-02-28 13:58:55 +0000 |
| commit | ce40d93b062c0bdcd29218c12ab1dba544382dd8 (patch) | |
| tree | 5d147838d7bee1592e613c028f565cbf710cb7bd /sound | |
| parent | ASoC: mt8192: Report an error if when an invalid sidetone gain is written (diff) | |
| download | wireguard-linux-ce40d93b062c0bdcd29218c12ab1dba544382dd8.tar.xz wireguard-linux-ce40d93b062c0bdcd29218c12ab1dba544382dd8.zip | |
ASoC: mt8192: Fix range for sidetone positive gain
The Sidetone_Positive_Gain_dB control reports a range of 0..100 as valid
but the put() function rejects anything larger than 24. Fix this.
There are numerous other problems with this control, the name is very non
idiomatic and it should be a TLV, but it's ABI so probably we should leave
those alone.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230223-asoc-mt8192-quick-fixes-v1-4-9a85f90368e1@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound')
| -rw-r--r-- | sound/soc/mediatek/mt8192/mt8192-dai-adda.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sound/soc/mediatek/mt8192/mt8192-dai-adda.c b/sound/soc/mediatek/mt8192/mt8192-dai-adda.c index a02a297c0450..4919535e2759 100644 --- a/sound/soc/mediatek/mt8192/mt8192-dai-adda.c +++ b/sound/soc/mediatek/mt8192/mt8192-dai-adda.c @@ -670,7 +670,7 @@ static int mt8192_adda6_only_set(struct snd_kcontrol *kcontrol, static const struct snd_kcontrol_new mtk_adda_controls[] = { SOC_SINGLE("Sidetone_Gain", AFE_SIDETONE_GAIN, SIDE_TONE_GAIN_SFT, SIDE_TONE_GAIN_MASK, 0), - SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 100, 0, + SOC_SINGLE_EXT("Sidetone_Positive_Gain_dB", SND_SOC_NOPM, 0, 24, 0, stf_positive_gain_get, stf_positive_gain_set), SOC_SINGLE("ADDA_DL_GAIN", AFE_ADDA_DL_SRC2_CON1, DL_2_GAIN_CTL_PRE_SFT, DL_2_GAIN_CTL_PRE_MASK, 0), |