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| author |   Junhui Liu <junhui.liu@pigmoral.tech> | 2025-10-21 17:41:45 +0800 |
|---|---|---|
| committer |   Conor Dooley <conor.dooley@microchip.com> | 2025-11-12 17:06:56 +0000 |
| commit | 9c96219602b1a29c1959c5799aa3e6c5e14e395c (patch) | |
| tree | 6da154a2b768e8b778727f07a332348a3d81aa78 /tools/lib/python/kdoc/python_version.py | |
| parent | dt-bindings: serial: snps-dw-apb-uart: Add Anlogic DR1V90 uart (diff) | |
riscv: Add Anlogic SoC famly Kconfig support
The first SoC in the Anlogic series is DR1V90, which contains a RISC-V
core from Nuclei.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'tools/lib/python/kdoc/python_version.py')
0 files changed, 0 insertions, 0 deletions