perf vendor events arm64: Add N1 metrics

Generated from the telemetry solution repo[1] with this command:

  ./generate.py <linux-repo>/tools/perf/ --telemetry-files \
    ../../data/pmu/cpu/neoverse/neoverse-n1.json

Since this data source now includes the SPE events for N1, it has
diverged from A76 which means the folder has to be split.

The new data also uses more fine grained grouping, but this will be
consistent for all future products. Long PublicDescriptions are now
included even for common events because this can include product
specific details. For non verbose mode the common BriefDescriptions
remain the same.

[1]: https://gitlab.arm.com/telemetry-solution/telemetry-solution

Signed-off-by: James Clark <james.clark@arm.com>
Acked-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mike Leach <mike.leach@linaro.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: renyu.zj@linux.alibaba.com
Link: https://lore.kernel.org/r/20230320114601.524958-1-james.clark@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

1 files changed, 24 insertions, 0 deletions

diff --git a/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/memory.json b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/memory.json
new file mode 100644
index 000000000000..5bed2514b245
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/memory.json
@@ -0,0 +1,24 @@
+[
+    {
+        "PublicDescription": "This event counts memory accesses due to load or store instructions. This event counts the sum of MEM_ACCESS_RD and MEM_ACCESS_WR.",
+        "ArchStdEvent": "MEM_ACCESS"
+    },
+    {
+        "ArchStdEvent": "REMOTE_ACCESS"
+    },
+    {
+         "ArchStdEvent": "MEM_ACCESS_RD"
+    },
+    {
+         "ArchStdEvent": "MEM_ACCESS_WR"
+    },
+    {
+         "ArchStdEvent": "UNALIGNED_LD_SPEC"
+    },
+    {
+         "ArchStdEvent": "UNALIGNED_ST_SPEC"
+    },
+    {
+         "ArchStdEvent": "UNALIGNED_LDST_SPEC"
+    }
+]