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author | Linus Torvalds <torvalds@linux-foundation.org> | 2019-11-26 15:04:47 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2019-11-26 15:04:47 -0800 |
commit | 3f59dbcace56fae7e4ed303bab90f1bedadcfdf4 (patch) | |
tree | c425529202b9dbe3e3b3dde072c1edf51b1b9e93 /tools/perf/pmu-events/arch/powerpc/power8/translation.json | |
parent | Merge branch 'efi-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip (diff) | |
parent | Merge branch 'x86/core' into perf/core, to resolve conflicts and to pick up completed topic tree (diff) | |
download | wireguard-linux-3f59dbcace56fae7e4ed303bab90f1bedadcfdf4.tar.xz wireguard-linux-3f59dbcace56fae7e4ed303bab90f1bedadcfdf4.zip |
Merge branch 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf updates from Ingo Molnar:
"The main kernel side changes in this cycle were:
- Various Intel-PT updates and optimizations (Alexander Shishkin)
- Prohibit kprobes on Xen/KVM emulate prefixes (Masami Hiramatsu)
- Add support for LSM and SELinux checks to control access to the
perf syscall (Joel Fernandes)
- Misc other changes, optimizations, fixes and cleanups - see the
shortlog for details.
There were numerous tooling changes as well - 254 non-merge commits.
Here are the main changes - too many to list in detail:
- Enhancements to core tooling infrastructure, perf.data, libperf,
libtraceevent, event parsing, vendor events, Intel PT, callchains,
BPF support and instruction decoding.
- There were updates to the following tools:
perf annotate
perf diff
perf inject
perf kvm
perf list
perf maps
perf parse
perf probe
perf record
perf report
perf script
perf stat
perf test
perf trace
- And a lot of other changes: please see the shortlog and Git log for
more details"
* 'perf-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (279 commits)
perf parse: Fix potential memory leak when handling tracepoint errors
perf probe: Fix spelling mistake "addrees" -> "address"
libtraceevent: Fix memory leakage in copy_filter_type
libtraceevent: Fix header installation
perf intel-bts: Does not support AUX area sampling
perf intel-pt: Add support for decoding AUX area samples
perf intel-pt: Add support for recording AUX area samples
perf pmu: When using default config, record which bits of config were changed by the user
perf auxtrace: Add support for queuing AUX area samples
perf session: Add facility to peek at all events
perf auxtrace: Add support for dumping AUX area samples
perf inject: Cut AUX area samples
perf record: Add aux-sample-size config term
perf record: Add support for AUX area sampling
perf auxtrace: Add support for AUX area sample recording
perf auxtrace: Move perf_evsel__find_pmu()
perf record: Add a function to test for kernel support for AUX area sampling
perf tools: Add kernel AUX area sampling definitions
perf/core: Make the mlock accounting simple again
perf report: Jump to symbol source view from total cycles view
...
Diffstat (limited to 'tools/perf/pmu-events/arch/powerpc/power8/translation.json')
-rw-r--r-- | tools/perf/pmu-events/arch/powerpc/power8/translation.json | 60 |
1 files changed, 30 insertions, 30 deletions
diff --git a/tools/perf/pmu-events/arch/powerpc/power8/translation.json b/tools/perf/pmu-events/arch/powerpc/power8/translation.json index e47a55459bc8..623e7475b010 100644 --- a/tools/perf/pmu-events/arch/powerpc/power8/translation.json +++ b/tools/perf/pmu-events/arch/powerpc/power8/translation.json @@ -1,176 +1,176 @@ [ - {, + { "EventCode": "0x4c054", "EventName": "PM_DERAT_MISS_16G", "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16G", "PublicDescription": "" }, - {, + { "EventCode": "0x3c054", "EventName": "PM_DERAT_MISS_16M", "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 16M", "PublicDescription": "" }, - {, + { "EventCode": "0x1c056", "EventName": "PM_DERAT_MISS_4K", "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 4K", "PublicDescription": "" }, - {, + { "EventCode": "0x2c054", "EventName": "PM_DERAT_MISS_64K", "BriefDescription": "Data ERAT Miss (Data TLB Access) page size 64K", "PublicDescription": "" }, - {, + { "EventCode": "0x4e048", "EventName": "PM_DPTEG_FROM_DL2L3_MOD", "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x3e048", "EventName": "PM_DPTEG_FROM_DL2L3_SHR", "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x1e042", "EventName": "PM_DPTEG_FROM_L2", "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x1e04e", "EventName": "PM_DPTEG_FROM_L2MISS", "BriefDescription": "A Page Table Entry was loaded into the TLB from a localtion other than the local core's L2 due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x2e040", "EventName": "PM_DPTEG_FROM_L2_MEPF", "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x1e040", "EventName": "PM_DPTEG_FROM_L2_NO_CONFLICT", "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x4e042", "EventName": "PM_DPTEG_FROM_L3", "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x3e042", "EventName": "PM_DPTEG_FROM_L3_DISP_CONFLICT", "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x2e042", "EventName": "PM_DPTEG_FROM_L3_MEPF", "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x1e044", "EventName": "PM_DPTEG_FROM_L3_NO_CONFLICT", "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x1e04c", "EventName": "PM_DPTEG_FROM_LL4", "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x2e048", "EventName": "PM_DPTEG_FROM_LMEM", "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x2e04c", "EventName": "PM_DPTEG_FROM_MEMORY", "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x4e04a", "EventName": "PM_DPTEG_FROM_OFF_CHIP_CACHE", "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x1e048", "EventName": "PM_DPTEG_FROM_ON_CHIP_CACHE", "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x2e046", "EventName": "PM_DPTEG_FROM_RL2L3_MOD", "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x1e04a", "EventName": "PM_DPTEG_FROM_RL2L3_SHR", "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x2e04a", "EventName": "PM_DPTEG_FROM_RL4", "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a data side request", "PublicDescription": "" }, - {, + { "EventCode": "0x300fc", "EventName": "PM_DTLB_MISS", "BriefDescription": "Data PTEG reload", "PublicDescription": "Data PTEG Reloaded (DTLB Miss)" }, - {, + { "EventCode": "0x1c058", "EventName": "PM_DTLB_MISS_16G", "BriefDescription": "Data TLB Miss page size 16G", "PublicDescription": "" }, - {, + { "EventCode": "0x4c056", "EventName": "PM_DTLB_MISS_16M", "BriefDescription": "Data TLB Miss page size 16M", "PublicDescription": "" }, - {, + { "EventCode": "0x2c056", "EventName": "PM_DTLB_MISS_4K", "BriefDescription": "Data TLB Miss page size 4k", "PublicDescription": "" }, - {, + { "EventCode": "0x3c056", "EventName": "PM_DTLB_MISS_64K", "BriefDescription": "Data TLB Miss page size 64K", "PublicDescription": "" }, - {, + { "EventCode": "0x200f6", "EventName": "PM_LSU_DERAT_MISS", "BriefDescription": "DERAT Reloaded due to a DERAT miss", "PublicDescription": "DERAT Reloaded (Miss)" }, - {, + { "EventCode": "0x20066", "EventName": "PM_TLB_MISS", "BriefDescription": "TLB Miss (I + D)", "PublicDescription": "" - }, + } ] |