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| author |   Ian Rogers <irogers@google.com> | 2023-03-24 00:22:10 -0700 |
|---|---|---|
| committer |   Arnaldo Carvalho de Melo <acme@redhat.com> | 2023-04-04 09:39:55 -0300 |
| commit | 7803654576db93c49be73ff02d53030558c971b7 (patch) | |
| tree | 409856ec79b31b34f90b2ab85dd30f7e2c6acd85 /tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json | |
| parent | perf lock contention: Fix msan issue in lock_contention_read() (diff) | |
| download | wireguard-linux-7803654576db93c49be73ff02d53030558c971b7.tar.xz wireguard-linux-7803654576db93c49be73ff02d53030558c971b7.zip | |
perf vendor events intel: Broadwell v27 events
Description updates and formatting changes.
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Samantha Alt <samantha.alt@intel.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20230324072218.181880-2-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json index ddcf7faa9d10..368a958a18a0 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json @@ -8,7 +8,7 @@ "Unit": "ARB" }, { - "BriefDescription": "Each cycle count number of all Core outgoing valid entries. Such entry is defined as valid from it's allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", + "BriefDescription": "Each cycle counts number of all Core outgoing valid entries. Such entry is defined as valid from its allocation till first of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-coherent traffic.", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", |