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| author |   Ingo Molnar <mingo@kernel.org> | 2018-12-03 11:22:00 +0100 |
|---|---|---|
| committer |   Arnaldo Carvalho de Melo <acme@redhat.com> | 2018-12-17 14:56:31 -0300 |
| commit | b1d6f155e1bbb67778c17aba661fb4ea4e1a3641 (patch) | |
| tree | b105cd284b34f1886e2a5cafcd8bbdf3504b9116 /tools/perf/pmu-events/arch/x86/sandybridge/cache.json | |
| parent | perf tests ARM: Disable breakpoint tests 32-bit (diff) | |
| download | wireguard-linux-b1d6f155e1bbb67778c17aba661fb4ea4e1a3641.tar.xz wireguard-linux-b1d6f155e1bbb67778c17aba661fb4ea4e1a3641.zip | |
perf vendor events intel: Fix diverse typos
Go over the tools/ files that are maintained in Arnaldo's tree and
fix common typos: half of them were in comments, the other half
in JSON files.
( Care should be taken not to re-import these typos in the future,
if the JSON files get updated by the vendor without fixing the typos. )
No change in functionality intended.
Committer notes:
This was split from a larger patch as there are code that is,
additionally, maintained outside the kernel tree, so to ease cherry
picking and/or backporting, split this into multiple patches.
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/20181203102200.GA104797@gmail.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/sandybridge/cache.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/sandybridge/cache.json | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json index bef73c499f83..16b04a20bc12 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json @@ -31,7 +31,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x41", @@ -42,7 +42,7 @@ }, { "PEBS": "1", - "PublicDescription": "This event counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", + "PublicDescription": "This event counts line-split store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).", "EventCode": "0xD0", "Counter": "0,1,2,3", "UMask": "0x42", |