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authorIan Rogers <irogers@google.com>2022-01-31 17:58:57 -0800
committerArnaldo Carvalho de Melo <acme@redhat.com>2022-02-14 21:16:56 -0300
commit4ad91126e649c59a7339c442482d113ed9a4c198 (patch)
tree60f2908c80fe820ee4a715af9573d324b5ebafe2 /tools/perf/pmu-events/arch/x86/westmereex/other.json
parentperf vendor events: Update Westmere EP-SP (diff)
downloadwireguard-linux-4ad91126e649c59a7339c442482d113ed9a4c198.tar.xz
wireguard-linux-4ad91126e649c59a7339c442482d113ed9a4c198.zip
perf vendor events: Update Westmere EX
Events are still at version 2: https://download.01.org/perfmon/WSM-EX Json files generated by the latest code at: https://github.com/intel/event-converter-for-linux-perf Tested: Not tested on a Westmere EX, on a SkylakeX: ... 9: Parse perf pmu format : Ok 10: PMU events : 10.1: PMU event table sanity : Ok 10.2: PMU event map aliases : Ok 10.3: Parsing of PMU event table metrics : Ok 10.4: Parsing of PMU event table metrics with fake PMUs : Ok ... Reviewed-by: Kan Liang <kan.liang@linux.intel.com> Signed-off-by: Ian Rogers <irogers@google.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.garry@huawei.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com> Link: https://lore.kernel.org/r/20220201015858.1226914-26-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/westmereex/other.json')
-rw-r--r--tools/perf/pmu-events/arch/x86/westmereex/other.json238
1 files changed, 119 insertions, 119 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/perf/pmu-events/arch/x86/westmereex/other.json
index 85133d6a5ce0..23dcd554728c 100644
--- a/tools/perf/pmu-events/arch/x86/westmereex/other.json
+++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json
@@ -1,287 +1,287 @@
[
{
- "EventCode": "0xE8",
+ "BriefDescription": "Early Branch Prediciton Unit clears",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xE8",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
- "BriefDescription": "Early Branch Prediciton Unit clears"
+ "UMask": "0x1"
},
{
- "EventCode": "0xE8",
+ "BriefDescription": "Late Branch Prediction Unit clears",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0xE8",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
- "BriefDescription": "Late Branch Prediction Unit clears"
+ "UMask": "0x2"
},
{
- "EventCode": "0xE5",
+ "BriefDescription": "Branch prediction unit missed call or return",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xE5",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
- "BriefDescription": "Branch prediction unit missed call or return"
+ "UMask": "0x1"
},
{
- "EventCode": "0xD5",
+ "BriefDescription": "ES segment renames",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xD5",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
- "BriefDescription": "ES segment renames"
+ "UMask": "0x1"
},
{
- "EventCode": "0x6C",
+ "BriefDescription": "I/O transactions",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x6C",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
- "BriefDescription": "I/O transactions"
+ "UMask": "0x1"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "L1I instruction fetch stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x4",
+ "EventCode": "0x80",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch stall cycles"
+ "UMask": "0x4"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "L1I instruction fetch hits",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x80",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch hits"
+ "UMask": "0x1"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "L1I instruction fetch misses",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0x80",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
- "BriefDescription": "L1I instruction fetch misses"
+ "UMask": "0x2"
},
{
- "EventCode": "0x80",
+ "BriefDescription": "L1I Instruction fetches",
"Counter": "0,1,2,3",
- "UMask": "0x3",
+ "EventCode": "0x80",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
- "BriefDescription": "L1I Instruction fetches"
+ "UMask": "0x3"
},
{
- "EventCode": "0x82",
+ "BriefDescription": "Large ITLB hit",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x82",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
- "BriefDescription": "Large ITLB hit"
+ "UMask": "0x1"
},
{
- "EventCode": "0x3",
+ "BriefDescription": "Loads that partially overlap an earlier store",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0x3",
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
"SampleAfterValue": "200000",
- "BriefDescription": "Loads that partially overlap an earlier store"
+ "UMask": "0x2"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "All loads dispatched",
"Counter": "0,1,2,3",
- "UMask": "0x7",
+ "EventCode": "0x13",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
- "BriefDescription": "All loads dispatched"
+ "UMask": "0x7"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "Loads dispatched from the MOB",
"Counter": "0,1,2,3",
- "UMask": "0x4",
+ "EventCode": "0x13",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched from the MOB"
+ "UMask": "0x4"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "Loads dispatched that bypass the MOB",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched that bypass the MOB"
+ "UMask": "0x1"
},
{
- "EventCode": "0x13",
+ "BriefDescription": "Loads dispatched from stage 305",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0x13",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
- "BriefDescription": "Loads dispatched from stage 305"
+ "UMask": "0x2"
},
{
- "EventCode": "0x7",
+ "BriefDescription": "False dependencies due to partial address aliasing",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0x7",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
- "BriefDescription": "False dependencies due to partial address aliasing"
+ "UMask": "0x1"
},
{
- "EventCode": "0xD2",
+ "BriefDescription": "All RAT stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0xf",
+ "EventCode": "0xD2",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
- "BriefDescription": "All RAT stall cycles"
+ "UMask": "0xf"
},
{
- "EventCode": "0xD2",
+ "BriefDescription": "Flag stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xD2",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
- "BriefDescription": "Flag stall cycles"
+ "UMask": "0x1"
},
{
- "EventCode": "0xD2",
+ "BriefDescription": "Partial register stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0xD2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
- "BriefDescription": "Partial register stall cycles"
+ "UMask": "0x2"
},
{
- "EventCode": "0xD2",
+ "BriefDescription": "ROB read port stalls cycles",
"Counter": "0,1,2,3",
- "UMask": "0x4",
+ "EventCode": "0xD2",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
- "BriefDescription": "ROB read port stalls cycles"
+ "UMask": "0x4"
},
{
- "EventCode": "0xD2",
+ "BriefDescription": "Scoreboard stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x8",
+ "EventCode": "0xD2",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
- "BriefDescription": "Scoreboard stall cycles"
+ "UMask": "0x8"
},
{
- "EventCode": "0x4",
+ "BriefDescription": "All Store buffer stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x7",
+ "EventCode": "0x4",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
- "BriefDescription": "All Store buffer stall cycles"
+ "UMask": "0x7"
},
{
- "EventCode": "0xD4",
+ "BriefDescription": "Segment rename stall cycles",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xD4",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
- "BriefDescription": "Segment rename stall cycles"
- },
- {
- "EventCode": "0xB8",
- "Counter": "0,1,2,3",
- "UMask": "0x1",
- "EventName": "SNOOP_RESPONSE.HIT",
- "SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HIT to snoop"
- },
- {
- "EventCode": "0xB8",
- "Counter": "0,1,2,3",
- "UMask": "0x2",
- "EventName": "SNOOP_RESPONSE.HITE",
- "SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HITE to snoop"
+ "UMask": "0x1"
},
{
- "EventCode": "0xB8",
+ "BriefDescription": "Snoop code requests",
"Counter": "0,1,2,3",
- "UMask": "0x4",
- "EventName": "SNOOP_RESPONSE.HITM",
- "SampleAfterValue": "100000",
- "BriefDescription": "Thread responded HITM to snoop"
- },
- {
"EventCode": "0xB4",
- "Counter": "0,1,2,3",
- "UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS.CODE",
"SampleAfterValue": "100000",
- "BriefDescription": "Snoop code requests"
+ "UMask": "0x4"
},
{
- "EventCode": "0xB4",
+ "BriefDescription": "Snoop data requests",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.DATA",
"SampleAfterValue": "100000",
- "BriefDescription": "Snoop data requests"
+ "UMask": "0x1"
},
{
- "EventCode": "0xB4",
+ "BriefDescription": "Snoop invalidate requests",
"Counter": "0,1,2,3",
- "UMask": "0x2",
+ "EventCode": "0xB4",
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
"SampleAfterValue": "100000",
- "BriefDescription": "Snoop invalidate requests"
+ "UMask": "0x2"
},
{
+ "BriefDescription": "Outstanding snoop code requests",
"EventCode": "0xB3",
- "UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
"SampleAfterValue": "2000000",
- "BriefDescription": "Outstanding snoop code requests"
+ "UMask": "0x4"
},
{
+ "BriefDescription": "Cycles snoop code requests queued",
+ "CounterMask": "1",
"EventCode": "0xB3",
- "UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
"SampleAfterValue": "2000000",
- "BriefDescription": "Cycles snoop code requests queued",
- "CounterMask": "1"
+ "UMask": "0x4"
},
{
+ "BriefDescription": "Outstanding snoop data requests",
"EventCode": "0xB3",
- "UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
"SampleAfterValue": "2000000",
- "BriefDescription": "Outstanding snoop data requests"
+ "UMask": "0x1"
},
{
+ "BriefDescription": "Cycles snoop data requests queued",
+ "CounterMask": "1",
"EventCode": "0xB3",
- "UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
"SampleAfterValue": "2000000",
- "BriefDescription": "Cycles snoop data requests queued",
- "CounterMask": "1"
+ "UMask": "0x1"
},
{
+ "BriefDescription": "Outstanding snoop invalidate requests",
"EventCode": "0xB3",
- "UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
"SampleAfterValue": "2000000",
- "BriefDescription": "Outstanding snoop invalidate requests"
+ "UMask": "0x2"
},
{
+ "BriefDescription": "Cycles snoop invalidate requests queued",
+ "CounterMask": "1",
"EventCode": "0xB3",
- "UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
"SampleAfterValue": "2000000",
- "BriefDescription": "Cycles snoop invalidate requests queued",
- "CounterMask": "1"
+ "UMask": "0x2"
},
{
- "EventCode": "0xF6",
+ "BriefDescription": "Thread responded HIT to snoop",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB8",
+ "EventName": "SNOOP_RESPONSE.HIT",
+ "SampleAfterValue": "100000",
+ "UMask": "0x1"
+ },
+ {
+ "BriefDescription": "Thread responded HITE to snoop",
"Counter": "0,1,2,3",
- "UMask": "0x1",
+ "EventCode": "0xB8",
+ "EventName": "SNOOP_RESPONSE.HITE",
+ "SampleAfterValue": "100000",
+ "UMask": "0x2"
+ },
+ {
+ "BriefDescription": "Thread responded HITM to snoop",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xB8",
+ "EventName": "SNOOP_RESPONSE.HITM",
+ "SampleAfterValue": "100000",
+ "UMask": "0x4"
+ },
+ {
+ "BriefDescription": "Super Queue full stall cycles",
+ "Counter": "0,1,2,3",
+ "EventCode": "0xF6",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
- "BriefDescription": "Super Queue full stall cycles"
+ "UMask": "0x1"
}
] \ No newline at end of file