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author | 2017-09-18 12:05:30 +0200 | |
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committer | 2017-09-24 13:08:48 +0100 | |
commit | 0a56eabc4e3f730782e4a9f3af4f60aa03a8a849 (patch) | |
tree | 4777099a1cb23ba0532eeea75f3561dcf260aed8 /tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py | |
parent | iio: adc: twl4030: Return an error if we can not enable the vusb3v1 regulator in 'twl4030_madc_probe()' (diff) | |
download | wireguard-linux-0a56eabc4e3f730782e4a9f3af4f60aa03a8a849.tar.xz wireguard-linux-0a56eabc4e3f730782e4a9f3af4f60aa03a8a849.zip |
iio: trigger: stm32-timer: preset shouldn't be buffered
Currently, setting preset value (ARR) will update directly 'Auto reload
value' only on 1st write access. But then, ARPE is set. This makes
ARR a shadow register. Preset value should be updated upon each
write request: ensure ARPE is 0. This fixes successive writes to
preset attribute.
Fixes: 4adec7da0536 ("iio: stm32 trigger: Add quadrature encoder device")
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Cc: <Stable@vger.kernel.org>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib/Perf/Trace/EventClass.py')
0 files changed, 0 insertions, 0 deletions