diff options
| author |   Ben Zong-You Xie <ben717@andestech.com> | 2025-07-11 21:30:22 +0800 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2025-07-21 16:51:52 +0200 |
| commit | 609496af55caff0e358bac901936b65b98900f92 (patch) | |
| tree | 2832c741a246573859540642b5493de49764c42d /tools/perf/scripts/python/Perf-Trace-Util/lib | |
| parent | dt-bindings: timer: add Andes machine timer (diff) | |
| download | wireguard-linux-609496af55caff0e358bac901936b65b98900f92.tar.xz wireguard-linux-609496af55caff0e358bac901936b65b98900f92.zip | |
riscv: dts: andes: add QiLai SoC device tree
Introduce the initial device tree support for the Andes QiLai SoC.
For further information, you can refer to [1].
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-7-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib')
0 files changed, 0 insertions, 0 deletions