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author | 2025-07-21 17:12:44 +0200 | |
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committer | 2025-07-21 17:13:33 +0200 | |
commit | 63e9bb0d6e03f59ff89d71f890a580c27b873ad2 (patch) | |
tree | c094f079f493f37d89086d25046411381012d7dc /tools/perf/scripts/python/Perf-Trace-Util/lib | |
parent | Merge branch 'newsoc/pxa1908' into soc/newsoc (diff) | |
parent | MAINTAINERS: Add entry for Andes SoC (diff) | |
download | wireguard-linux-63e9bb0d6e03f59ff89d71f890a580c27b873ad2.tar.xz wireguard-linux-63e9bb0d6e03f59ff89d71f890a580c27b873ad2.zip |
Merge branch 'newsoc/andes' into soc/newsoc
Patches from Ben Zong-You Xie <ben717@andestech.com>:
The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
including Andes QiLai SoC. This patch series adds minimal device tree
files for the QiLai SoC and the Voyager board [1].
Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
[2] https://lore.kernel.org/all/20250602060747.689824-1-ben717@andestech.com/
* newsoc/andes:
MAINTAINERS: Add entry for Andes SoC
riscv: defconfig: enable Andes SoC
riscv: dts: andes: add Voyager board device tree
riscv: dts: andes: add QiLai SoC device tree
dt-bindings: timer: add Andes machine timer
dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
dt-bindings: interrupt-controller: add Andes QiLai PLIC
dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
riscv: add Andes SoC family Kconfig support
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib')
0 files changed, 0 insertions, 0 deletions