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| author |   Timur Kristóf <timur.kristof@gmail.com> | 2025-07-31 11:43:46 +0200 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2025-08-18 17:57:45 -0400 |
| commit | cb7b7ae53b557d168b4af5cd8549f3eff920bfb5 (patch) | |
| tree | bc972bc127287eca6164d106fecb78213fe85878 /tools/perf/scripts/python/Perf-Trace-Util/lib | |
| parent | drm/amd/display: Add null pointer check in mod_hdcp_hdcp1_create_session() (diff) | |
| download | wireguard-linux-cb7b7ae53b557d168b4af5cd8549f3eff920bfb5.tar.xz wireguard-linux-cb7b7ae53b557d168b4af5cd8549f3eff920bfb5.zip | |
drm/amd/display: Don't overclock DCE 6 by 15%
The extra 15% clock was added as a workaround for a Polaris issue
which uses DCE 11, and should not have been used on DCE 6 which
is already hardcoded to the highest possible display clock.
Unfortunately, the extra 15% was mistakenly copied and kept
even on code paths which don't affect Polaris.
This commit fixes that and also adds a check to make sure
not to exceed the maximum DCE 6 display clock.
Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
Fixes: 3ecb3b794e2c ("drm/amd/display: dc/clk_mgr: add support for SI parts (v2)")
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
Reviewed-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
(cherry picked from commit 427980c1cbd22bb256b9385f5ce73c0937562408)
Cc: stable@vger.kernel.org
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util/lib')
0 files changed, 0 insertions, 0 deletions