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| author |   Ben Zong-You Xie <ben717@andestech.com> | 2025-07-11 21:30:19 +0800 |
|---|---|---|
| committer |   Arnd Bergmann <arnd@arndb.de> | 2025-07-21 16:51:52 +0200 |
| commit | 6eeee4fb1930a3863911cf3b620ec340c9227952 (patch) | |
| tree | 06b47bc81add340dd75b402d33aa97fba0a0056d /tools/perf/scripts/python/Perf-Trace-Util | |
| parent | dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings (diff) | |
| download | wireguard-linux-6eeee4fb1930a3863911cf3b620ec340c9227952.tar.xz wireguard-linux-6eeee4fb1930a3863911cf3b620ec340c9227952.zip | |
dt-bindings: interrupt-controller: add Andes QiLai PLIC
Add a new compatible string for Andes QiLai PLIC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-4-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'tools/perf/scripts/python/Perf-Trace-Util')
0 files changed, 0 insertions, 0 deletions