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| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2025-06-09 23:56:28 +0100 |
|---|---|---|
| committer |   Biju Das <biju.das.jz@bp.renesas.com> | 2025-06-12 19:42:28 +0100 |
| commit | a56a6b81d80fdf876a5ee6e441a6c8a0052f6f37 (patch) | |
| tree | ff53767b936bd1723f458c2c3f0ce906495b5cb3 /tools/perf/scripts/python/arm-cs-trace-disasm.py | |
| parent | drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations (diff) | |
| download | wireguard-linux-a56a6b81d80fdf876a5ee6e441a6c8a0052f6f37.tar.xz wireguard-linux-a56a6b81d80fdf876a5ee6e441a6c8a0052f6f37.zip | |
drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support
Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.
Update the `mipi_dsi_host_attach()` function to check this flag before
allowing 16BPP formats. If the SoC does not support 16BPP, return an error
to prevent incorrect format selection.
This change enables finer-grained format support control for different
SoC variants.
Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20250609225630.502888-8-prabhakar.mahadev-lad.rj@bp.renesas.com
Diffstat (limited to 'tools/perf/scripts/python/arm-cs-trace-disasm.py')
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