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| author | 2026-04-11 16:14:15 -0700 | |
|---|---|---|
| committer | 2026-04-11 16:14:15 -0700 | |
| commit | 0fc42d26467f2b3321aa3cc57f97350e1e04ecb9 (patch) | |
| tree | dee8e49f7fa809e6ceed51d77c5c681933ac4059 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | Linux 7.0-rc5 (diff) | |
| parent | clk: rockchip: rk3568: Add PCIe pipe clock gates (diff) | |
Merge tag 'v7.1-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip
Pull Rockchip clk driver updates from Heiko Stuebner:
- Clock driver for the Rockchip RV1103B SoC
For whatever reason that SoC only got a B addition to the name,
but major changes internally - likely it is pin compatible with
the non-b-variant. Other change is actually exporting PCIe
pipe-clocks that were already in the binding.
* tag 'v7.1-rockchip-clk1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3568: Add PCIe pipe clock gates
clk: rockchip: Add clock controller for the RV1103B
dt-bindings: clock: rockchip: Add RV1103B CRU support
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions
