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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2026-03-26 19:45:42 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2026-03-26 19:45:42 +0100 |
| commit | 30e7ff3598bb9d686a6e56a56b06cf2f07180bef (patch) | |
| tree | 612757a6489ae64d6e0e3a59d56c2e04eaadc170 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | clk: renesas: rzg2l: Re-enable critical module clocks during resume (diff) | |
| parent | dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3L SoC (diff) | |
Merge tag 'renesas-r9a08g046-dt-binding-defs-tag1' into renesas-clk-for-v7.1
Renesas RZ/G3L DT Binding Definitions
DT bindings and binding definitions for the Renesas RZ/G3L (R9A08G046)
SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
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