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| author |   Jason-JH Lin <jason-jh.lin@mediatek.com> | 2025-10-31 23:56:33 +0800 |
|---|---|---|
| committer |   AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> | 2026-01-19 12:57:45 +0100 |
| commit | 5ea617e818333a2078dadc11e5734886e39901d0 (patch) | |
| tree | ca43c272f8eb428a17ba1a2e9f3b7b15003b1a3b /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction (diff) | |
mailbox: mtk-cmdq: Add driver data to support for MT8196
MT8196 has 2 new hardware configuration compared with the previous SoC,
which correspond to the 2 new driver data:
1. mminfra_offset: For GCE data path control
Since GCE has been moved into mminfra, GCE needs to append the
mminfra offset to the DRAM address when accessing the DRAM.
2. gce_vm: For GCE hardware virtualization control
Currently, the first version of the mt8196 mailbox controller only
requires setting the VM-related registers to enable the permissions
of a host VM.
Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions