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| author |   Jouni Högander <jouni.hogander@intel.com> | 2026-03-04 13:30:09 +0200 |
|---|---|---|
| committer |   Tvrtko Ursulin <tursulin@ursulin.net> | 2026-03-10 08:22:10 +0000 |
| commit | c2c79c6d5b939ae8a42ddb884f576bddae685672 (patch) | |
| tree | 5637fa1772848bed8f1f9c2aef08b0061797df4c /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | drm/i915/psr: Repeat Selective Update area alignment (diff) | |
drm/i915/dsc: Add Selective Update register definitions
Add definitions for DSC_SU_PARAMETER_SET_0_DSC0 and
DSC_SU_PARAMETER_SET_0_DSC1 registers. These are for Selective Update Early
Transport configuration.
Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Link: https://patch.msgid.link/20260304113011.626542-3-jouni.hogander@intel.com
(cherry picked from commit 24f96d903daf3dcf8fafe84d3d22b80ef47ba493)
Signed-off-by: Tvrtko Ursulin <tursulin@ursulin.net>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions