diff options
| author |   Ovidiu Panait <ovidiu.panait.rb@renesas.com> | 2026-01-25 19:27:02 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2026-03-06 13:33:56 +0100 |
| commit | c8d5972a25408b1daf73653ccd5207fdfc80c964 (patch) | |
| tree | a6c88d5b9dafe3f84e8a0a5af8b23dd4ec4a0bd8 /tools/perf/scripts/python/bin/stackcollapse-record | |
| parent | clk: renesas: r9a09g057: Remove entries for WDT{0,2,3} (diff) | |
clk: renesas: r9a09g056: Add clock and reset entries for RTC
Add module clock and reset entries for the RTC module on the Renesas
RZ/V2N (R9A09G056) SoC.
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260125192706.27099-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/bin/stackcollapse-record')
0 files changed, 0 insertions, 0 deletions