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| author |   Ovidiu Panait <ovidiu.panait.rb@renesas.com> | 2026-01-25 19:27:01 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2026-02-24 08:51:34 +0100 |
| commit | dc71d92f0d36dcb68fcf0ef126131a2dedef9393 (patch) | |
| tree | d1e2201e643406683370b49afd9e13b0653ae841 /tools/perf/scripts/python/bin | |
| parent | clk: renesas: r9a09g057: Fix ordering of module clocks array (diff) | |
clk: renesas: r9a09g056: Fix ordering of module clocks array
The r9a09g056_mod_clks array is sorted by CPG_CLKON register number and
bit position. Move the RSPI 0/1/2 module clock entries to their correct
position to restore the array sort order.
Fixes: 1f76689d1715 ("clk: renesas: r9a09g056: Add entries for RSCIs")
Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260125192706.27099-2-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/bin')
0 files changed, 0 insertions, 0 deletions