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author | 2024-06-15 17:03:53 +0000 | |
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committer | 2024-07-29 21:02:03 +0200 | |
commit | 1d34b9757523c1ad547bd6d040381f62d74a3189 (patch) | |
tree | 712f7c30bfb315fc92c1a7b45c2ff201a9908b20 /tools/perf/scripts/python/call-graph-from-postgresql.py | |
parent | Linux 6.11-rc1 (diff) | |
download | wireguard-linux-1d34b9757523c1ad547bd6d040381f62d74a3189.tar.xz wireguard-linux-1d34b9757523c1ad547bd6d040381f62d74a3189.zip |
clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228
Similar to DCLK_LCDC on RK3328, the DCLK_VOP on RK3228 is typically
parented by the hdmiphy clk and it is expected that the DCLK_VOP and
hdmiphy clk rate are kept in sync.
Use CLK_SET_RATE_PARENT and CLK_SET_RATE_NO_REPARENT flags, same as used
on RK3328, to make full use of all possible supported display modes.
Fixes: 0a9d4ac08ebc ("clk: rockchip: set the clock ids for RK3228 VOP")
Fixes: 307a2e9ac524 ("clk: rockchip: add clock controller for rk3228")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Link: https://lore.kernel.org/r/20240615170417.3134517-3-jonas@kwiboo.se
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions