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authorManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>2024-03-21 16:46:39 +0530
committerBjorn Andersson <andersson@kernel.org>2024-04-21 12:28:49 -0500
commit27cb9eccf94cb163f9bf3b945f249ab7c42861db (patch)
treed03850a07ae7ea485ae36de42bdb846bf05d94f2 /tools/perf/scripts/python/call-graph-from-postgresql.py
parentARM: dts: qcom: ipq4019: Add PCIe bridge node (diff)
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wireguard-linux-27cb9eccf94cb163f9bf3b945f249ab7c42861db.zip
ARM: dts: qcom: apq8064: Add PCIe bridge node
On Qcom SoCs, the PCIe host bridge is connected to a single PCIe bridge for each controller instance. Hence, add a node to represent the bridge. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240321-pcie-qcom-bridge-dts-v2-19-1eb790c53e43@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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