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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-11-06 23:58:52 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2024-11-28 17:59:50 +0200 |
| commit | 57ecdc5521831b179d34109a74f993371fb2730e (patch) | |
| tree | d9a9926cb4ee82b28641a17eec2a6495e7debc4b /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | drm/i915/dsb: Nuke the MMIO->indexed register write logic (diff) | |
| download | wireguard-linux-57ecdc5521831b179d34109a74f993371fb2730e.tar.xz wireguard-linux-57ecdc5521831b179d34109a74f993371fb2730e.zip | |
drm/i915/pps: Store the power cycle delay without the +1
The code initializing the power sequencing delays is a bit
hard to follow. One confusing thing is that we keep doing the
+/-1 adjustment for the hardware register value in several places.
Simplify this a bit by doing the adjustment only when reading or
writing the actual register.
This also matches how the LVDS code does things.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241106215859.25446-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions