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author | 2017-01-20 07:52:23 +0100 | |
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committer | 2017-02-07 13:52:51 +0900 | |
commit | 5aa6c9ace55d2ca2d41118208fe8476907b4b066 (patch) | |
tree | b6b97cfc0b1ce3de8046dff0e77f6e89b8c0d7bf /tools/perf/scripts/python/call-graph-from-postgresql.py | |
parent | drm/exynos/hdmi: fix PLL for 27MHz settings (diff) | |
download | wireguard-linux-5aa6c9ace55d2ca2d41118208fe8476907b4b066.tar.xz wireguard-linux-5aa6c9ace55d2ca2d41118208fe8476907b4b066.zip |
drm/exynos/decon5433: add support for interlace modes
Some registers should be programmed differently in interlace mode.
Additionally IP does not signal stop state properly in interlaced
mode, so warning has been removed.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions