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| author |   Neil Armstrong <neil.armstrong@linaro.org> | 2023-11-24 09:41:17 +0100 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2023-11-24 17:07:40 +0100 |
| commit | 5de4e8353e321c9b91be4233ab99527c4930bfe9 (patch) | |
| tree | 6cce63fba75f27098ff6fb59191698fdd55bb8b2 /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | dt-bindings: clk: g12a-clkc: add CTS_ENCL clock ids (diff) | |
| download | wireguard-linux-5de4e8353e321c9b91be4233ab99527c4930bfe9.tar.xz wireguard-linux-5de4e8353e321c9b91be4233ab99527c4930bfe9.zip | |
clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks
Add new CTS_ENCL & CTS_ENCL_SEL clocks for the G12A compatible
SoCs, they are used to feed the VPU LCD Pixel encoder used for
DSI display purposes.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231124-amlogic-v6-4-upstream-dsi-ccf-vim3-v9-6-95256ed139e6@linaro.org
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions