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| author |   Abin Joseph <abin.joseph@amd.com> | 2024-10-09 21:58:21 +0530 |
|---|---|---|
| committer |   Jakub Kicinski <kuba@kernel.org> | 2024-10-11 15:41:33 -0700 |
| commit | 60dbdc6e08d6fe66380598ef8bb857a4474e30d9 (patch) | |
| tree | 2aee90420206311b111e315f3be9bd91f7c96cfa /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | Merge branch 'net-remove-rtnl-from-fib_seq_sum' (diff) | |
| download | wireguard-linux-60dbdc6e08d6fe66380598ef8bb857a4474e30d9.tar.xz wireguard-linux-60dbdc6e08d6fe66380598ef8bb857a4474e30d9.zip | |
dt-bindings: net: emaclite: Add clock support
Add s_axi_aclk AXI4 clock support. Traditionally this IP was used on
microblaze platforms which had fixed clocks enabled all the time. But
since its a PL IP, it can also be used on SoC platforms like Zynq
UltraScale+ MPSoC which combines processing system (PS) and user
programmable logic (PL) into the same device. On these platforms instead
of fixed enabled clocks it is mandatory to explicitly enable IP clocks
for proper functionality.
So make clock a required property and also define max supported clock
constraints.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/1728491303-1456171-2-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions