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| author |   Jiancheng Xue <xuejiancheng@hisilicon.com> | 2016-04-23 15:40:30 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2016-05-06 11:13:32 -0700 |
| commit | 6c9da387c8d5c5254857d2782bd6c314226f4f27 (patch) | |
| tree | 3189ede959921db199f190d8aed8b8ab2fde692a /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | clk: hisilicon: export some hisilicon APIs to modules (diff) | |
| download | wireguard-linux-6c9da387c8d5c5254857d2782bd6c314226f4f27.tar.xz wireguard-linux-6c9da387c8d5c5254857d2782bd6c314226f4f27.zip | |
clk: hisilicon: add CRG driver for hi3519 soc
The CRG(Clock and Reset Generator) block provides clock
and reset signals for other modules in hi3519 soc.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions