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authorRohit Agarwal <rohiagar@chromium.org>2024-08-30 08:45:43 +0000
committerMatthias Brugger <matthias.bgg@gmail.com>2024-09-09 16:41:36 +0200
commit7a3852a9ba2e40738fa4ddadb4e94ae68f3826a4 (patch)
tree6a3659e88181459eabe5907bb64e8d0298bfa868 /tools/perf/scripts/python/call-graph-from-postgresql.py
parentarm64: dts: mediatek: mt8195: Correct clock order for dp_intf* (diff)
downloadwireguard-linux-7a3852a9ba2e40738fa4ddadb4e94ae68f3826a4.tar.xz
wireguard-linux-7a3852a9ba2e40738fa4ddadb4e94ae68f3826a4.zip
arm64: dts: mediatek: mt8186: Add power domain for DPI
Add power domain phandle to the DPI controller in mediatek mt8186 SoC. Signed-off-by: Rohit Agarwal <rohiagar@chromium.org> Link: https://lore.kernel.org/r/20240830084544.2898512-3-rohiagar@chromium.org Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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