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| author |   Biju Das <biju.das.jz@bp.renesas.com> | 2024-12-13 12:35:40 +0000 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2025-01-07 17:00:03 +0100 |
| commit | 9b6e63a777ea5fb85bf24f9cb5ba902eed4f1f2f (patch) | |
| tree | a956dea656a5531b38a8d0faa676b95afd407b7e /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ADC IP (diff) | |
| download | wireguard-linux-9b6e63a777ea5fb85bf24f9cb5ba902eed4f1f2f.tar.xz wireguard-linux-9b6e63a777ea5fb85bf24f9cb5ba902eed4f1f2f.zip | |
clk: renesas: rzv2h: Add MSTOP support
Add MSTOP support to control buses for the individual units on RZ/V2H.
Use per-bit (instead of group-based) configuration and atomic counters,
to ensure precise control over individual MSTOP bits, and to prevent
issues with shared dependencies between module clocks.
Co-developed-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20241213123550.289193-2-biju.das.jz@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Link: https://lore.kernel.org/20250102181839.352599-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions