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author | 2024-06-23 22:03:00 +0200 | |
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committer | 2024-06-25 19:55:58 +0300 | |
commit | d6c7c411be788d1cf78a4fdec3ce080a8f2e39e1 (patch) | |
tree | c433f6d2ffb703aebc53ff0dfa4b6ed87a00978e /tools/perf/scripts/python/call-graph-from-postgresql.py | |
parent | drm/msm/dpu: remove CRTC frame event callback registration (diff) | |
download | wireguard-linux-d6c7c411be788d1cf78a4fdec3ce080a8f2e39e1.tar.xz wireguard-linux-d6c7c411be788d1cf78a4fdec3ce080a8f2e39e1.zip |
dt-bindings: display/msm/gpu: constrain clocks in top-level
We expect each schema with variable number of clocks, to have the widest
constrains in top-level "properties:". This is more readable and also
makes binding stricter, if there is no "if:then:" block for given
variant.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/600504/
Link: https://lore.kernel.org/r/20240623-qcom-adreno-dts-bindings-driver-v2-1-9496410de992@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
0 files changed, 0 insertions, 0 deletions