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| author |   Jakub Kicinski <kuba@kernel.org> | 2024-10-11 15:41:36 -0700 |
|---|---|---|
| committer | Jakub Kicinski <kuba@kernel.org> | 2024-10-11 15:41:37 -0700 |
| commit | f7cb403e9a6929c13547dc6329716110edc8bfe7 (patch) | |
| tree | 27da57097ddb485e8ccec748da189b945e19138f /tools/perf/scripts/python/call-graph-from-postgresql.py | |
| parent | Merge branch 'net-remove-rtnl-from-fib_seq_sum' (diff) | |
| parent | net: emaclite: Adopt clock support (diff) | |
| download | wireguard-linux-f7cb403e9a6929c13547dc6329716110edc8bfe7.tar.xz wireguard-linux-f7cb403e9a6929c13547dc6329716110edc8bfe7.zip | |
Merge branch 'net-xilinx-emaclite-adopt-clock-support'
Radhey Shyam Pandey says:
====================
net: xilinx: emaclite: Adopt clock support
This patchset adds emaclite clock support. AXI Ethernet Lite IP can also
be used on SoC platforms like Zynq UltraScale+ MPSoC which combines
powerful processing system (PS) and user-programmable logic (PL) into
the same device. On these platforms it is mandatory to explicitly enable
IP clocks for proper functionality.
====================
Link: https://patch.msgid.link/1728491303-1456171-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-postgresql.py')
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