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| author |   Michal Simek <michal.simek@xilinx.com> | 2016-04-07 11:28:12 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2017-08-21 13:52:56 +0200 |
| commit | 1188c024f2163dc065177b3f20b508902df36960 (patch) | |
| tree | 540ecdf93529708c72b1a782c0c48bfe8ba54c8e /tools/perf/scripts/python/call-graph-from-sql.py | |
| parent | arm: zynq: Label whole PL part as fpga_full region (diff) | |
| download | wireguard-linux-1188c024f2163dc065177b3f20b508902df36960.tar.xz wireguard-linux-1188c024f2163dc065177b3f20b508902df36960.zip | |
arm: zynq: Use C pre-processor for includes in dts
Change the dtsi include code to use the C pre-processor #include instead
of the device tree /include/. This brings all Zynq device trees inline
with each other.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Diffstat (limited to 'tools/perf/scripts/python/call-graph-from-sql.py')
0 files changed, 0 insertions, 0 deletions