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| author |   Po-Yu Chuang <ratbert.chuang@gmail.com> | 2013-06-07 12:15:45 +0100 |
|---|---|---|
| committer |   Russell King <rmk+kernel@arm.linux.org.uk> | 2013-06-17 10:30:50 +0100 |
| commit | 37468b30a3948bbbdf9d664678f611510d987e65 (patch) | |
| tree | d46579a471170b90f709125c35bec5c3dbe1bbc3 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | ARM: 7752/1: errata: LoUIS bit field in CLIDR register is incorrect (diff) | |
| download | wireguard-linux-37468b30a3948bbbdf9d664678f611510d987e65.tar.xz wireguard-linux-37468b30a3948bbbdf9d664678f611510d987e65.zip | |
ARM: 7753/1: map_init_section flushes incorrect pmd
This bug was introduced in commit e651eab0.
Some v4/v5 platforms failed to boot due to this.
Signed-off-by: Po-Yu Chuang <ratbert.chuang@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions