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| author |   Clément Léger <cleger@rivosinc.com> | 2023-10-04 17:14:05 +0200 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2023-11-01 08:34:59 -0700 |
| commit | 9f23a5d2f6b01c2ab91d791109731a0d87ec2239 (patch) | |
| tree | 17fd1a240636a03de468a1f01b0ca407f099de28 /tools/perf/scripts/python/check-perf-trace.py | |
| parent | riscv: report misaligned accesses emulation to hwprobe (diff) | |
| download | wireguard-linux-9f23a5d2f6b01c2ab91d791109731a0d87ec2239.tar.xz wireguard-linux-9f23a5d2f6b01c2ab91d791109731a0d87ec2239.zip | |
riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
Now that trap support is ready to handle misalignment errors in S-mode,
allow the user to control the behavior of misaligned accesses using
prctl(PR_SET_UNALIGN). Add an align_ctl flag in thread_struct which
will be used to determine if we should SIGBUS the process or not on
such fault.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Björn Töpel <bjorn@rivosinc.com>
Link: https://lore.kernel.org/r/20231004151405.521596-9-cleger@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/check-perf-trace.py')
0 files changed, 0 insertions, 0 deletions