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| author |   Vignesh R <vigneshr@ti.com> | 2017-10-03 10:49:21 +0530 |
|---|---|---|
| committer |   Cyrille Pitchen <cyrille.pitchen@wedev4u.fr> | 2017-10-17 20:38:27 +0200 |
| commit | 61dc8493bae9ba82a1c72edbc6c6065f6a94456a (patch) | |
| tree | 39eacded0ae461dc2df6e4c8709f574ab5009423 /tools/perf/scripts/python/compaction-times.py | |
| parent | mtd: spi-nor: cadence-quadspi: Add TI 66AK2G SoC specific compatible (diff) | |
| download | wireguard-linux-61dc8493bae9ba82a1c72edbc6c6065f6a94456a.tar.xz wireguard-linux-61dc8493bae9ba82a1c72edbc6c6065f6a94456a.zip | |
mtd: spi-nor: cadence-quadspi: add a delay in write sequence
As per 66AK2G02 TRM[1] SPRUHY8F section 11.15.5.3 Indirect Access
Controller programming sequence, a delay equal to couple of QSPI master
clock(~5ns) is required after setting CQSPI_REG_INDIRECTWR_START bit and
writing data to the flash. Introduce a quirk flag CQSPI_NEEDS_WR_DELAY
to handle this and set this flag for TI 66AK2G SoC.
[1]http://www.ti.com/lit/ug/spruhy8f/spruhy8f.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions