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| author |   Colin Xu <colin.xu@intel.com> | 2018-06-11 15:39:34 +0800 |
|---|---|---|
| committer |   Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-06-13 10:57:29 +0800 |
| commit | a94cf2e0ef7fef5cb42ed96f73c18c3ad4f0d170 (patch) | |
| tree | e1705b04b994227f82d5517c5ff093d4a3ec1a58 /tools/perf/scripts/python/compaction-times.py | |
| parent | drm/i915/gvt: Enable irq initialization for BXT. (diff) | |
| download | wireguard-linux-a94cf2e0ef7fef5cb42ed96f73c18c3ad4f0d170.tar.xz wireguard-linux-a94cf2e0ef7fef5cb42ed96f73c18c3ad4f0d170.zip | |
drm/i915/gvt: Enable mmio context init and switch for BXT.
Handle pending tlb flush, mocs/mmio switch and context as KBL.
Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'tools/perf/scripts/python/compaction-times.py')
0 files changed, 0 insertions, 0 deletions