diff options
| author |   Paul Kocialkowski <paulk@sys-base.io> | 2025-07-01 22:11:23 +0200 |
|---|---|---|
| committer |   Chen-Yu Tsai <wens@csie.org> | 2025-07-03 23:31:05 +0800 |
| commit | 01fdcbc7e5a56c9cba521e0f237cb5c3fd162432 (patch) | |
| tree | 68c7002389b04b9031c6061bc34188c3acaac675 /tools/perf/scripts/python/event_analyzing_sample.py | |
| parent | clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name (diff) | |
| download | wireguard-linux-01fdcbc7e5a56c9cba521e0f237cb5c3fd162432.tar.xz wireguard-linux-01fdcbc7e5a56c9cba521e0f237cb5c3fd162432.zip | |
clk: sunxi-ng: v3s: Fix TCON clock parents
The TCON clock can be parented to both the video PLL and the periph0 PLL.
Add the latter, which was missing from the list.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
Link: https://patch.msgid.link/20250701201124.812882-5-paulk@sys-base.io
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Diffstat (limited to 'tools/perf/scripts/python/event_analyzing_sample.py')
0 files changed, 0 insertions, 0 deletions