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| author |   Palmer Dabbelt <palmerdabbelt@google.com> | 2021-06-30 21:50:32 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-06-30 21:50:32 -0700 |
| commit | 01112e5e20f5298a81639806cd0a3c587aade467 (patch) | |
| tree | b453c32b2e3a8905da331a81ad234c17b62cb9dc /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: Enable KFENCE for riscv64 (diff) | |
| parent | riscv: Map the kernel with correct permissions the first time (diff) | |
| download | wireguard-linux-01112e5e20f5298a81639806cd0a3c587aade467.tar.xz wireguard-linux-01112e5e20f5298a81639806cd0a3c587aade467.zip | |
Merge branch 'riscv-wx-mappings' into for-next
This contains both the short-term fix for the W+X boot mappings and the
larger cleanup.
* riscv-wx-mappings:
riscv: Map the kernel with correct permissions the first time
riscv: Introduce set_kernel_memory helper
riscv: Simplify xip and !xip kernel address conversion macros
riscv: Remove CONFIG_PHYS_RAM_BASE_FIXED
riscv: mm: Fix W+X mappings at boot
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions