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| author |   Dmitry Rokosov <ddrokosov@sberdevices.ru> | 2023-05-23 16:53:46 +0300 |
|---|---|---|
| committer |   Jerome Brunet <jbrunet@baylibre.com> | 2023-05-30 17:52:52 +0200 |
| commit | 02f1e17c4106a24fabb27e1419cbcb144b4faa1b (patch) | |
| tree | ca222384db48be171b6c1fef797dbfb029dc4e51 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: clock: meson: add A1 Peripherals clock controller bindings (diff) | |
| download | wireguard-linux-02f1e17c4106a24fabb27e1419cbcb144b4faa1b.tar.xz wireguard-linux-02f1e17c4106a24fabb27e1419cbcb144b4faa1b.zip | |
clk: meson: make pll rst bit as optional
Compared with the previous SoCs, self-adaption current module
is newly added for A1, and there is no reset parameter except the
fixed pll. Since we use clk-pll generic driver for A1 pll
implementation, rst bit should be optional to support new behavior.
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Link: https://lore.kernel.org/r/20230523135351.19133-2-ddrokosov@sberdevices.ru
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions