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| author |   Hugo Villeneuve <hvilleneuve@dimonoff.com> | 2024-01-16 16:29:58 -0500 |
|---|---|---|
| committer |   Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-01-27 19:09:09 -0800 |
| commit | 0419373333c2f2024966d36261fd82a453281e80 (patch) | |
| tree | 54cfcc40770a560a4146d7fc970873dce087386b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | serial: core: Fix atomicity violation in uart_tiocmget (diff) | |
| download | wireguard-linux-0419373333c2f2024966d36261fd82a453281e80.tar.xz wireguard-linux-0419373333c2f2024966d36261fd82a453281e80.zip | |
serial: max310x: set default value when reading clock ready bit
If regmap_read() returns a non-zero value, the 'val' variable can be left
uninitialized.
Clear it before calling regmap_read() to make sure we properly detect
the clock ready bit.
Fixes: 4cf9a888fd3c ("serial: max310x: Check the clock readiness")
Cc: stable@vger.kernel.org
Signed-off-by: Hugo Villeneuve <hvilleneuve@dimonoff.com>
Link: https://lore.kernel.org/r/20240116213001.3691629-2-hugo@hugovil.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions