diff options
| author |   Samuel Holland <samuel.holland@sifive.com> | 2024-02-27 22:55:35 -0800 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-02-29 10:20:18 -0800 |
| commit | 05ab803d1ad8ac505ade77c6bd3f86b1b4ea0dc4 (patch) | |
| tree | d8b4e6641bbc4ccdcdee992a84b84f0fb46c5293 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: Add a custom ISA extension for the [ms]envcfg CSR (diff) | |
| download | wireguard-linux-05ab803d1ad8ac505ade77c6bd3f86b1b4ea0dc4.tar.xz wireguard-linux-05ab803d1ad8ac505ade77c6bd3f86b1b4ea0dc4.zip | |
riscv: Save/restore envcfg CSR during CPU suspend
The value of the [ms]envcfg CSR is lost when entering a nonretentive
idle state, so the CSR must be rewritten when resuming the CPU.
Cc: <stable@vger.kernel.org> # v6.7+
Fixes: 43c16d51a19b ("RISC-V: Enable cbo.zero in usermode")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Link: https://lore.kernel.org/r/20240228065559.3434837-4-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions